Recently, along with the advances in technology for fabrication of semiconductor integrated circuits, circuits have been improved in their degree of integration. Further, the same semiconductor chip (semiconductor device) is now being used to mount a plurality of circuits.
On the other hand, semiconductor devices (LSI) are being widely used for mobile phones and other devices driven by battery power. Along with recent efforts to save energy, therefore, a greater reduction in the power consumption of semiconductor devices has become desired.
Along with such recent demands for reduction of the power consumption of LSIs, the technique of intentionally lowering the operating frequency (clock frequency) for lighter load circuits so as to reduce the power consumption has been utilized.
Further, the technique of lowering the supply voltage to individual circuit blocks in accordance with the load of each circuit block in an LSI, that is, dynamic voltage and frequency scaling (DVFS), is also starting to be employed.
Furthermore, semiconductor devices which mount low drop output regulators (LDO) which supply the plurality of circuits inside the semiconductor devices with voltages which are obtained by lowering the power source voltage which is input from the outside have also been proposed.
As explained above, in recent years, various techniques have been proposed for lowering the power consumption of LSIs. Commensurate effects have been achieved. However, for example, if providing a DC-DC converter for each circuit block so as to control the power source voltage, a large increase in costs will be incurred.
Further, even in LSIs which are designed to control the voltage value of the supply voltage or the clock frequency in accordance with the load of the individual circuit blocks, greater reduction of the power consumption is being sought.
Patent Document 1: Japanese Laid-open Patent Publication No. 2005-235223
Patent Document 2: Japanese Laid-open Patent Publication No. 2004-005670
Patent Document 3: Japanese National Publication of International Patent Application No. 2001-517332
Non-Patent Document 1: H. Mair, et al., “A 65-nm Mobile Multimedia Applications Processor with an Adaptive Power Management Scheme to Compensate for Variations,” Symposium on VLSI Circuits Digest Technical Papers, Paper 21-5, pp. 224-225, June, 2007